1. Field of the Invention
The claimed invention discloses a sensing circuit, and more particularly, to a sensing circuit for a memory cell supplied with low power.
2. Description of the Prior Art
In a conventional memory cell, a stored bit is programmed or erased so that the memory cell can be used for consecutively storing different bits. The memory cell has a program state for programming the stored bit and an erase state for erasing the stored bit from the memory cell. Under a program state of the memory cell, an output current of the memory cell is higher, whereas under the erase state of the memory cell, the output current of the memory cell is lower. Note that the output current of the memory cell is highly-related to a cross voltage of the memory cell. For accurately reading the stored bit from the memory cell under both the programming state and the erasing state, a latch-type circuit is designed for sensing the output current of the memory cell so as to distinguish the program state from the erase state.
For distinguishing the program state from the erase state, transition of the program state and the erase state of the memory cell has to be carefully handled. The latch-type circuit outputs different digital signals respectively corresponding to the program state and the erase state according to two different levels of voltages.
Please refer to FIG. 1, which illustrates a conventional latch-type circuit 10 for telling the program state and the erase state for a memory cell. As shown in FIG. 1, latch-type circuit 10 includes a first P-type transistor P1, a second P-type transistor P2, a fuse 12, and an N-type transistor N1. A node A1, which is located between a first terminal of the fuse 12 and a drain of the first P-type transistor P1, is connected to an output terminal of a memory cell, which is not illustrated in FIG. 1, for sensing an output current of the memory cell so as to recognize the program state and the erase state of the memory cell. While the memory cell is under the erase state, the fuse 12 is open-circuited so that the first N-type transistor N1 is switched on, and the second P-type transistor P2 is switched off. Therefore, an output voltage Vout at the drain of the first N-type transistor is low to indicate the erase state. Note that the fuse 12 may have its resistance. While the memory cell is then transited from the erase state to the program state, the fuse 12 is short-circuited so that the first N-type transistor N1 is switched off, and the second P-type transistor P2 is switched on. Therefore, the output voltage Vout is high to indicate the program state.
Assume that the second P-type transistor P2 has an threshold voltage Vthp, therefore, while the fuse 12 is short-circuited under the erase state and the memory cell is going to be transited to the program state, the voltage at the node A1 has to be lower than (Vdd-Vthp) for switching on the second P-type transistor P2. For a conventional memory cell, getting a voltage at the node A1 with a magnitude lower than (Vdd-Vthp) is easy, however, for memory cells having significantly smaller scales, the supplied power Vdd is getting much lower so that the voltage at the node A1 is barely lower than the voltage difference (Vdd-Vthp); as a result, the second P-type transistor P2 cannot be switched on from the erase state to the program state, and the entire operation of the memory cell may thus fail. In other words, while designing the memory cell, the supplied voltage Vdd meets restrictions in its lower bound, and it is not beneficial in reducing the size of memory cell.
Please refer FIG. 2, which illustrates a conventional latch circuit 20 for distinguishing the program state from the erase state of a memory cell. As shown in FIG. 2, the latch circuit 20 includes a second N-type transistor N2, a third P-type transistor P3, a third N-type transistor N3, and a fuse 22. Similar with the latch-type circuit 10 shown in FIG. 1, a node A2 connected to both a first terminal of the fuse 22 and a drain of the second N-type transistor N2 is connected to the output terminal of the memory cell mentioned in FIG. 1 and is not shown in FIG. 2. Under the program state of the memory cell, the fuse 22 is short-circuited so that a voltage at the node A2 is high, and therefore, the third P-type transistor P3 is switched off whereas the third N-type transistor N3 is switched on; as a result, the voltage Vout is low for indicating the program state of the memory cell. While the memory cell is then transited from the program state to the erase state, the fuse 22 is open-circuited so that the voltage at the node A2 is low so that the third P-type transistor P3 is switched on whereas the third N-type transistor N3 is switched off. A threshold voltage of the third N-type transistor N3 is assumed to be Vthn. Similarly, while the fuse 22 is short-circuited under the erase state and the memory cell is going to be transited to the program state, the voltage at the node A2 has to be higher than Vthn for switching on the third N-type transistor N3; however, if the supplied voltage Vdd is too low because of a reducing scale of the memory cell, the voltage at the node A2 may not be high enough to switch on the third N-type transistor N3, and the erase state cannot be activated from the program state as a result.